1. Field of the Invention
The present invention relates to a method for forming a twin gate CMOS, wherein small dimension and more quality fabrication can 10 be achieved.
2. Description of the Prior Art
In the conventional method for manufacturing twin gate transistors, the gates of the transistor are first defined on an undoped conducting layer, generally, followed by a channel implantation, which forms the source/drain terminals such that the conducting layer of the gate is doped in situ to increase its electrical conductivity. With the current trend of heavy reduction of semiconductor component dimensions in integrated circuits and the importance of preventing the short channel effect in the transistors due to excessive thickness in the source/drain diffusion regions, such layers have had to become thinner and thinner; and as a result, the impurity concentration resulting from channel implantation is also necessarily becoming lighter and lighter. Therefore, after the ion doping operation the impurity concentration in the conducting layer of the gate may be insufficient, which leads to an increase in sheet resistance and may affect both its electrical conductivity and the threshold voltage (Vt) level of the transistor.
In an improved version of the conventional method of fabricating a twin gate CMOS, in order to lessen the effects on threshold voltage level caused by low impurity concentration in the gates of the twin gate transistor, a heavier doping of impurities is performed in situ with the formation of the conducting layer of the transistor. The details of such a method are illustrated in FIGS. 1A through 1G.
First, referring to FIG. 1A, a P-well 140 and a N-well 160, with an isolating region 180 there between, are formed adjacent to each other on a P-type silicon substrate 100. Then the isolating region 180 is formed of an insulating material such as silicon dioxide. Next, a thermal oxidation method is used to form a gate oxide layer 200 on the substrate surface, and thereafter, chemical vapor deposition (CVD) is used to form a conductive layer 210 above the gate oxide layer 200. The conductive layer 210, for example, can be a polysilicon layer formed by deposition using disilane gas (Si.sub.2 H.sub.6) and with P-type ion doping, for example, using diborane (B.sub.2 H.sub.6), performed in situ for convening the polysilicon layer into a P.sup.+ -type polysilicon layer 210. Then, a first photoresist layer 230 is formed over the surface of the P.sup.+ -type polysilicon layer 210 above the N-type well 160.
Referring to FIG. 1B, in a subsequent step the exposed P.sup.+ -type polysilicon layer 210 is etched until the upper surface of the gate oxide layer 200 is exposed. Then, the first photoresist layer 230 is removed. The CVD is again used to form a polysilicon layer 250 on the surfaces of the exposed gate oxide layer 200 and P.sup.+ -type polysilicon layer 210. The deposition uses disilane gas with N-type ion doping, for example, PH.sub.3 performed in situ doped, to convert the polysilicon layer into an N.sup.+ -type polysilicon layer 250.
Referring next to FIG. 1C, in the subsequent step a second photoresist layer 270 is formed over the surface of the N.sup.+ -type polysilicon layer 250 above the P-type well region 140, and then is etched back until the upper surface of the P.sup.+ -type polysilicon layer 210 is exposed.
Referring next to FIG. 1D, the second photoresist layer 270 is removed. Then, using a conventional photolithographic technique, a third photoresist layer 290 is formed above the respective N.sup.+ -type 250 and P.sup.+ -type polysilicon layer 210 as a mask for defining the gates in subsequent steps. Due to misalignment of photoresist layer 270, there may be a gap in between the N.sup.+ -type 250 and P.sup.+ -type polysilicon layer 210 in the following etch step.
Referring next to FIG. 1E, with the third photoresist layer as a mask, the P.sup.+ and N.sup.+ type polysilicon layers are etched to mark out a P.sup.+ -type polysilicon gate 330 and an N.sup.+ -type polysilicon gate 310, and then the third photoresist layer is removed. Sequentially, under high heat and in a steamy environment, thin layer of oxide 500P and 500N are formed on the respective surfaces of the P.sup.+ -type 330 and N.sup.+ -type polysilicon gate 310. Next, a conventional photolithographic technique is again used to form a fourth photoresist layer 370 over the surface of the gate oxide layer SOOP above the N-type well regions 160 and covering up the P.sup.+ -type polysilicon gate 330. Subsequently, N-type ions, for example, arsenic ions 390I, is used in a channel implantation process, to form N.sup.+ -type source/drain of diffusion regions 390 on the substrate surface, on each side of the N.sup.+ -type polysilicon gate 310, thus completing the NMOS part of the CMOS component.
Referring next to FIG. 1F, in the subsequent step a fifth photoresist layer 410 is formed over the surface of the thin oxide layer 500N above the P-type well 140 and covering up the N.sup.+ -type polysilicon gate terminal 310. Subsequently, P-type ions, for example, boron fluoride ions 430I, is used in a channel implantation process, to forming P.sup.+ -type source/drain of diffusion regions 430 on the substrate surface on each side of the P.sup.+ -type polysilicon gate 330, thus completing the PMOS part of the CMOS component. Next, referring to FIG. 1G, the fifth photoresist layer 410 is removed to complete the twin gate transistor.
Although the improved method for fabricating conventional twin-gate CMOS mentioned previously can solve the problem of unstable threshold voltage causes by low doping density for twin-gate, there still comes with the following disadvantages. For in-situ doped P.sup.+ -type gates, due to the high doping concentration at the interface between a P.sup.+ -type polysilicon layer and a gate oxide layer, boron ions might easily penetrate through the gate oxide layer, hence, results in a shifting of the threshold voltage. Moreover, referring to what is shown in FIG. 1C, when taking photoresist 270 as a mask to etch N.sup.+ -type polysilicon layer, it is easy to result in a disconnection between P.sup.+ -type and N.sup.+ -type polysilicon layer, like what is shown in FIG. 1D, due to the mis-alignment of photoresist 270. Thus, this disconnection will result in an entire circuit malfunction in CMOS circuits wherein P.sup.+ -type and N.sup.+ -type polysilicon layer connections are usually needed.